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Reports (Research Report) Year : 1994

VSDF : Synchronous Data Flow for VLSI


This article describes a modified Synchronous Data Flow model which is suitable for modeling synchronous VLSI circuits. The target model takes advantage of the synchronous nature of the operations to eliminate buffering between circuits where possible. We introduce a temporal notation, and define functions relevant to constructing a system.


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inria-00074339 , version 1 (24-05-2006)


  • HAL Id : inria-00074339 , version 1


Alain Kerihuel, Roderick Mcconnell, Sanjay Rajopadhye. VSDF : Synchronous Data Flow for VLSI. [Research Report] RR-2337, INRIA. 1994. ⟨inria-00074339⟩
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