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Reports Year : 2002

High Throughput Implementations of the RC6 Block Cipher Using Virtex-E and Virtex-II Devices

Abstract

This short paper is devoted to the study of effective hardware architectures for the RC6 block cipher using Virtex-E and Virtex-II FPGA devices. The key point of the implementation is the design of an arithmetic operator computing f(X)=(X(2X+1))2^w. Significant speed and area improvements are obtained by taking full advantage of the small multiplier blocks available in Virtex-II devices.

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Other [cs.OH]
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Dates and versions

inria-00072093 , version 1 (23-05-2006)

Identifiers

  • HAL Id : inria-00072093 , version 1

Cite

Jean-Luc Beuchat. High Throughput Implementations of the RC6 Block Cipher Using Virtex-E and Virtex-II Devices. RR-4495, INRIA. 2002. ⟨inria-00072093⟩
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