Reciprocal Square Root Accelerated Using Hardware and Software Techniques
Résumé
The square root function is an elementary function with wide-ranging applications, particularly in the field of vector mathematics. One of the common variants is the reciprocal square root, used to compute the Euclidean norm of a vector during normalisation. In this process, each vector coefficient is divided by the norm to ensure that the resulting vector has a length of one. This normalisation is essential for various graphical transformations. It is also used to accelerate training with batch normalisation. Squaring the reciprocal square root can be used to compute the reciprocal, and multiplying it by the input to compute the square root. The square root function and its variants are already hardware accelerated in most processors, including Kalray's where one square root function can be computed per cycle in the core. This leads to two issues. First, when intensive computations are carried out within the accelerator, going back and forth with the core for every computation is not ideal. Secondly, the throughput of one function approximation per cycle is too low for an accelerator that manipulates a vector of 8 FP32 numbers, even worse for the reciprocal square root if it is computed in two step. This leads to the need of a new accelerator-specific way of implementing the family of square root functions, using a mix of hardware and software accelerations. This presentation proposes a method to accelerate the reciprocal square root, the square root and the reciprocal function using one hardware operator based on multipartite tables, and software refinements as needed to fit the required accuracy target.