Testing Resource Isolation for System-on-Chip Architectures - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2024

Testing Resource Isolation for System-on-Chip Architectures

Résumé

Ensuring resource isolation at the hardware level is a crucial step towards more security inside the Internet of Things. Even though there is still no generally accepted technique to generate appropriate tests, it became clear that tests should be generated at the system level. In this paper, we illustrate the modeling aspects in test generation for resource isolation, namely modeling the behavior and expressing the intended test scenario. We present both aspects using the industrial standard PSS and an academic approach based on conformance testing.
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Dates et versions

hal-04573384 , version 1 (13-05-2024)

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Philippe Ledent, Radu Mateescu, Wendelin Serwe. Testing Resource Isolation for System-on-Chip Architectures. MARS 2024 - 6th Workshop on Models for Formal Analysis of Real Systems, Apr 2024, Luxembourg, Luxembourg. pp.1-40, ⟨10.48550/arXiv.2403.18720⟩. ⟨hal-04573384⟩
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