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Resource Optimal Squarers for FPGAs

Andreas Böttcher
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Martin Kumm
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Squaring is an essential operation in computer arithmetic that can be considered as a special case of multiplication where several simplifications can be applied to reduce the complexity of the resulting circuit. However, the design of a squarer is not straightforward for modern FPGAs that provide embedded DSP blocks and look-up-tables (LUTs). This work proposes a flexible method to design resource optimal squarers, i.e., a squarer that uses a minimum number of LUTs for a userdefined number of DSP blocks. The method uses an integer linear programming (ILP) formulation based on a generalization of multiplier tiling. It is shown that the proposed squarer design method significantly improves the LUT utilization for a given number of DSPs over previous methods, while maintaining a similar critical path delay and latency.
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Dates and versions

hal-03922311 , version 1 (04-01-2023)



Andreas Böttcher, Martin Kumm, Florent de Dinechin. Resource Optimal Squarers for FPGAs. International Conference on Field-Programmable Logic and Applications (FPL), Aug 2022, Belfast, United Kingdom. ⟨10.1109/FPL57034.2022.00018⟩. ⟨hal-03922311⟩
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