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Communication Dans Un Congrès Année : 2021

Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI

Résumé

A very low-power 875 MS/s 7b single-channel high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a SNDR/SFDR at Nyquist rate of 41.46/55.01 dB is presented. The use of an integer-based split CDAC combined with an improvement for the LSB capacitor allows a substantial improvement in the SNDR. A simple and accurate calibration procedure for the ADC is presented thanks to back gate biasing. The ADC is designed in 22 nm FDSOI while consuming 1.65 mW from a 0.8 V supply with a core chip area of 0.00074 mm$$^2$$2. The Walden figure-of-merit of 19.5 fJ/conversion-step at Nyquist rate making it one of the lowest among recently published medium resolution SAR ADCs.
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hal-03759737 , version 1 (24-08-2022)

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David Cordova, Wim Cops, Yann Deval, François Rivet, Herve Lapuyade, et al.. Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI. 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2020, Salt Lake City, UT, United States. pp.1-19, ⟨10.1007/978-3-030-81641-4_1⟩. ⟨hal-03759737⟩
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