A Simple Analysis to Determine the Limits of a CMOS Technology to Implement SC DC-DC Converters
Résumé
This paper presents a simple analysis that allows to determine the maximum power density and efficiency of a SC DC-DC converter for a given CMOS technology. By determining the values of the ratio between the switches’ gate capacitance and channel width, and between the ON resistance and the channel width, together with the parasitic capacitances from the flying capacitors, it is possible to plot the efficiency as a function of the power density for a given input and output voltage of the converter, allowing to quickly determine both the expected efficiency and clock frequency ranges of the converter, for a given CMOS technology.
Domaines
Informatique [cs]Origine | Fichiers produits par l'(les) auteur(s) |
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