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Conference Papers Year : 2018

Model-checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits

Abstract

Asynchronous circuits have key advantages in terms of low energy consumption, robustness, and security. However , the absence of a global clock makes the design prone to deadlock, livelock, synchronization, and resource-sharing errors. Formal verification is thus essential for designing such circuits, but it is not widespread enough, as many hardware designers are not familiar with it and few verification tools can cope with asyn-chrony on complex designs. This paper suggests how an industrial design flow for asynchronous circuits, based upon the standard HDL SystemVerilog, can be supplemented with formal verification capabilities rooted in concurrency theory and model-checking technology. We demonstrate the practicality of our approach on an industrial asynchronous circuit (4000 lines of SystemVerilog) implementing a memory protection unit.
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Dates and versions

hal-01777093 , version 1 (24-04-2018)

Identifiers

  • HAL Id : hal-01777093 , version 1

Cite

Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu, Wendelin Serwe. Model-checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. ASYNC'18 - 24th IEEE International Symposium on Asynchronous Circuits and Systems , May 2018, Vienne, Austria. ⟨hal-01777093⟩
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