Embedding the V-Detector Algorithm in FPGA - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2016

Embedding the V-Detector Algorithm in FPGA

Maciej Brzozowski
  • Function : Author
  • PersonId : 994968
Andrzej Chmielewski
  • Function : Author
  • PersonId : 994969

Abstract

The b-v model is a hybrid immune-based approach for detecting anomalies in high-dimensional datasets. It is based on a negative selection algorithm and utilizes both types of detectors to achieve better results in comparison to single detection models. Also, it is an interesting alternative to well known traditional, statistical approaches, because only positive (self) examples are required at the learning stage. As a result, it is able to detect even unnkown or never met anomalies and this fact is one of the most attractive features of this approach. However, especially in the case of on-line classification, not only high accuracy but also high efficiency is needed. Thus, we propose to embed some complex tasks in a reprogrammable FPGA to offload CPU and speed up the classification process. This paper presents a hardware implementation of the V-Detector algorithm, which is the most complex and time consuming part of b-v model.
Fichier principal
Vignette du fichier
419526_1_En_5_Chapter.pdf (812.49 Ko) Télécharger le fichier
Origin : Files produced by the author(s)
Loading...

Dates and versions

hal-01637459 , version 1 (17-11-2017)

Licence

Attribution

Identifiers

Cite

Maciej Brzozowski, Andrzej Chmielewski. Embedding the V-Detector Algorithm in FPGA. 15th IFIP International Conference on Computer Information Systems and Industrial Management (CISIM), Sep 2016, Vilnius, Lithuania. pp.43-54, ⟨10.1007/978-3-319-45378-1_5⟩. ⟨hal-01637459⟩
26 View
64 Download

Altmetric

Share

Gmail Facebook X LinkedIn More