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Conference Papers Year : 2017

Hardware-Accelerated Dynamic Binary Translation


Dynamic Binary Translation (DBT) is often used in hardware/software co-design to take advantage of an architecture model while using binaries from another one. The co-development of the DBT engine and of the execution architecture leads to architecture with special support to these mechanisms. In this work, we propose a hardware accelerated Dynamic Binary Translation where the first steps of the DBT process are fully accelerated in hardware. Results shows that using our hardware accelerators leads to a speed-up of 8$\times$ and a cost in energy 18x lower, compared with an equivalent software approach.
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Dates and versions

hal-01423639 , version 1 (03-04-2017)


  • HAL Id : hal-01423639 , version 1


Simon Rokicki, Erven Rohou, Steven Derrien. Hardware-Accelerated Dynamic Binary Translation. IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland. ⟨hal-01423639⟩
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