Hardware-Accelerated Dynamic Binary Translation - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2017

Hardware-Accelerated Dynamic Binary Translation

Abstract

Dynamic Binary Translation (DBT) is often used in hardware/software co-design to take advantage of an architecture model while using binaries from another one. The co-development of the DBT engine and of the execution architecture leads to architecture with special support to these mechanisms. In this work, we propose a hardware accelerated Dynamic Binary Translation where the first steps of the DBT process are fully accelerated in hardware. Results shows that using our hardware accelerators leads to a speed-up of 8$\times$ and a cost in energy 18x lower, compared with an equivalent software approach.
Fichier principal
Vignette du fichier
rokicki_DATE_cr.pdf (316.29 Ko) Télécharger le fichier
DATE2017.pdf (1.42 Mo) Télécharger le fichier
Origin : Files produced by the author(s)
Origin : Files produced by the author(s)
Loading...

Dates and versions

hal-01423639 , version 1 (03-04-2017)

Identifiers

  • HAL Id : hal-01423639 , version 1

Cite

Simon Rokicki, Erven Rohou, Steven Derrien. Hardware-Accelerated Dynamic Binary Translation. IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland. ⟨hal-01423639⟩
1012 View
1964 Download

Share

Gmail Facebook X LinkedIn More