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Conference Papers Year : 2014

A 0.5 V Ultra-low Power Quadrature Ring Oscillator


In this paper we present a CMOS quadrature ring oscillator operating at 0.5 V. Due to this very low voltage conditions, new project technique using the available terminal of the transistors (bulk) is used in order to reduce the threshold voltage of the transistors, thus improving the voltage headroom. The technique is applied in a conventional inverter-based ring oscillator with a feedback topology capable to generate quadrature signals. Simulations results in a 130 nm CMOS technology shows that a very simple VCO in the GHz range can be obtained, by changing the bulk voltage of transistors (NMOS or PMOS). The circuit operates with less than 50 μW achieving a FoM of about -115 dBc/Hz at 10 MHz offset.
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hal-01274825 , version 1 (16-02-2016)





João Eusébio, Luís B. Oliveira, Luís Miguel Pires, João P. Oliveira. A 0.5 V Ultra-low Power Quadrature Ring Oscillator. 5th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Apr 2014, Costa de Caparica, Portugal. pp.575-581, ⟨10.1007/978-3-642-54734-8_64⟩. ⟨hal-01274825⟩
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