Towards Modeling and Simulation of Exascale Computing Platforms
Abstract
Future super-computer platforms will be facing big challenges due to
the enormous power consumption. One possible solution to this problem
would be to develop HPC systems from today’s energy-efficient hardware
solutions used in embedded and mobile devices like ARM. However, ARM
chips have never been used in HPC programing before, leading to a number
of significant challenges. Therefore, we experimented with ARM processors
and compared their performance with the architectures that are known
better, in this case last generations of Intel processors. Due to the memory
bottleneck of most scientific applications, understanding the performance
of CPU caches in this context is crucial, thus this research was investigat-
ing the processor performance depending on memory hierarchy. We present
not only differences and complexity of these two architectures, but also how
changing seemingly innocuous aspects of an experimental setup can cause
completely distinctive behavior. Additionally, we demonstrate very clean
and systematic methodology, which aid us in achieving good performance
estimations.
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Master_Report.pdf (780.21 Ko)
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Presentation.pdf (1.43 Mo)
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