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Conference Papers Year : 2014

Sum-of-Product Architectures Computing Just Right

Abstract

Many digital filters and signal-processing transforms can be expressed as a sum of products with constants (SPC). This paper addresses the automatic construction of low-precision, but high accuracy SPC architectures: these architectures are specified as last-bit accurate with respect to a mathematical definition. In other words, they behave as if the computation was performed with infinite accuracy, then rounded only once to the low-precision output format. This eases the task of porting double-precision code (e.g. Matlab) to low-precision hardware or FPGA. The paper further discusses the construction of the most efficient architectures obeying such a specification, introducing several architectural improvements to this purpose. This approach is demonstrated in a generic, open-source architecture generator tool built upon the FloPoCo framework. It is evaluated on Finite Impulse Response filters for the ZigBee protocol.
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Dates and versions

hal-00957609 , version 1 (10-03-2014)

Identifiers

  • HAL Id : hal-00957609 , version 1

Cite

Florent de Dinechin, Matei Istoan, Albdelbassat Massouri. Sum-of-Product Architectures Computing Just Right. ASAP - Application-specific Systems, Architectures and Processors, Jun 2014, Zurich, Switzerland. ⟨hal-00957609⟩
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