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Conference Papers Year : 2011

Scalable Fixed-Point Free Instruction Cache Analysis

Damien Hardy
Benjamin Lesage
  • Function : Author
  • PersonId : 881369
Isabelle Puaut

Abstract

Estimating worst-case execution times (WCETs) for architectures with caches requires the worst-case number of cache misses to be upper bounded. Most existing static cache analysis methods use fixed-point computation and do not scale well with large code sizes. To address this scalability issue, we propose in this paper a new fast and scalable instruction cache analysis technique. In contrast to existing work, neither fixed- point computation nor heavyweight interprocedural analysis are required. Thus, code sizes too long to analyze with existing techniques are then analyzable with lower analysis time and memory consumption, and with only a slight degradation of the analysis precision. Experimental results show a reduction of the analysis execution time of a factor 5 in average (with a peak near 30 for the largest and most complex code) with only a degradation of the analysis precision of 0.5% in average. The proposed technique is intended to be used in situations where the need for fast analysis outweighs the need for very tight results: early software development phases, timing analysis of large pieces of software, or iterative WCET-oriented compiler optimizations.
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Dates and versions

inria-00638698 , version 1 (07-11-2011)

Identifiers

  • HAL Id : inria-00638698 , version 1

Cite

Damien Hardy, Benjamin Lesage, Isabelle Puaut. Scalable Fixed-Point Free Instruction Cache Analysis. The 32nd IEEE Real-Time Systems Symposium (RTSS 2011), Nov 2011, Vienne, Austria. ⟨inria-00638698⟩
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