Task placement for dynamic and partial reconfigurable architecture - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2010
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inria-00536714 , version 1 (16-11-2010)

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  • HAL Id : inria-00536714 , version 1

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Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Task placement for dynamic and partial reconfigurable architecture. Conference on Design and Architectures for Signal and Image Processing, Oct 2010, Edimbourg, United Kingdom. ⟨inria-00536714⟩
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