A simple, verified validator for software pipelining - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2010

A simple, verified validator for software pipelining


Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class performances characteristics, but at the cost of significant obfuscation of the code, making this optimization difficult to test and debug. In this paper, we present a translation validation algorithm that uses symbolic evaluation to detect semantics discrepancies between a loop and its pipelined version. Our algorithm can be implemented simply and efficiently, is provably sound, and appears to be complete with respect to most modulo scheduling algorithms. A conclusion of this case study is that it is possible and effective to use symbolic evaluation to reason about loop transformations.
Fichier principal
Vignette du fichier
validation-softpipe.pdf (354.1 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

inria-00529836 , version 1 (26-10-2010)



Jean-Baptiste Tristan, Xavier Leroy. A simple, verified validator for software pipelining. 37th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2010, Jan 2010, Madrid, Spain. ⟨10.1145/1706299.1706311⟩. ⟨inria-00529836⟩


134 View
251 Download



Gmail Facebook X LinkedIn More