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Conference Papers Year : 2011

A low-area yet performant FPGA implementation of Shabal


In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throughput of 2 Gbit/s at a cost of only 153 slices, yielding a throughput-vs.-area ratio of 13.4 Mbit/s per slice. Our work can also be ported to Xilinx Spartan-3 FPGAs, on which it supports a throughput of 800 Mbit/s for only 499 slices, or equivalently 1.6 Mbit/s per slice. According to the SHA-3 Zoo website, this work is among the smallest reported FPGA implementations of SHA-3 candidates, and ranks first in terms of throughput per area.
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inria-00498705 , version 1 (08-07-2010)



Jérémie Detrey, Pierrick Gaudry, Karim Khalfallah. A low-area yet performant FPGA implementation of Shabal. 17th International Workshop on Selected Areas in Cryptography, SAC 2010, Aug 2010, Waterloo, Canada. pp.99-113, ⟨10.1007/978-3-642-19574-7_7⟩. ⟨inria-00498705⟩
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