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Conference Papers Year : 2010

MadCache: A PC-aware Cache Insertion Policy


While the field of computer architecture is always looking for novel research directions to bring improved performance and efficiency, it is often simple improvements to more mature topics that have the most substantial impact. Cache replacement policy is one such research area, where innovations are highly sought after because of their direct improvement on performance. Furthermore, as chip-multiprocessors have become the dominant chip design, new cache replacement schemes should seek to improve the performance of workloads for both singlethreaded and shared cache multithreaded systems. In this paper we propose MadCache, a cache insertion policy that uses memory access history based on the Program Counter (PC) to determine the appropriate policy for the L3 cache. A PC-based history table stores information regarding cache accesses and determines whether the L3 should default to the LRU replacement policy for workloads that exhibit good locality or bypass for streaming memory accesses. Furthermore, this PC-based history table allows individual PCs to override this default policy if its history indicates a behavior significantly different from the typical trend of the workload. We show that MadCache is able to improve IPC by 2.5% over LRU for a singlethreaded 1MB 16-way L3 cache. Finally, we extend MadCache to a four thread, 4MB shared L3 cache and demonstrate a 6% improvement in throughput and 4.5% speedup over LRU averaged across the mixed benchmarks we tested.
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Dates and versions

inria-00492989 , version 1 (17-06-2010)


  • HAL Id : inria-00492989 , version 1


Mitchell Hayenga, Andrew Nere, Mikko Lipasti. MadCache: A PC-aware Cache Insertion Policy. JWAC 2010 - 1st JILP Worshop on Computer Architecture Competitions: cache replacement Championship, Jun 2010, Saint Malo, France. ⟨inria-00492989⟩


ISCA2010 JWAC2010
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