G729 voice decoder design - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Journal Articles Journal of Signal Processing Systems Year : 2006

G729 voice decoder design


Embedded digital signal processing (DSP) systems are usually associated with real time constraints and/or high data rates such that fully software implementations are often not satisfactory. In that case, mixed hardware/software implementations are to be investigated. This paper presents the design of a HW/SW G.729 voice decoder dedicated to embedded systems. The decoder has been built around, on the one hand a reconfigurable digital circuit (FPGA) to achieve the so called IP hardware part - the autocorrelation computation - using a linear systolic array, and on the other hand a digital signal processor (DSP) for the remainder of the algorithm. Apart such an implementation is typically driven by the use of reusable component (IP) it is of great interest for new G729-based applications such as Voice over IP (VoIP) for example. It results in an overall reduction of the execution time per frame. Another interesting point is the design of a parameterizable autocorrelation block which can be useful for a wide range of applications such as GSM 13Kbit/s, APC 9,6 Kbit/s and G723 6.3 Kbit/s and 5.3 Kbit/s. In the G729 context and using a V50 Virtex FPGA, the execution time of this function is 10 times faster than a TMS320C6201 DSP implementation.
No file

Dates and versions

inria-00477377 , version 1 (28-04-2010)


  • HAL Id : inria-00477377 , version 1


Fatma Sayadi, Emmanuel Casseau, Rached Tourki, Eric Martin. G729 voice decoder design. Journal of Signal Processing Systems, 2006, 42 (2), pp.173-184. ⟨inria-00477377⟩
193 View
0 Download


Gmail Facebook Twitter LinkedIn More