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Article Dans Une Revue International Journal of Electronics Année : 2008

Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval

Résumé

With ever larger and more affordable storage capabilities, individuals and companies can now collect huge amounts of multimedia data, especially images. Searching such databases is still an open problem, known as content-based image retrieval (CBIR). In this paper, we present a hardware architecture based on FPGAs which aims at speeding-up visual CBIR. Our architecture is based on the unique combination of reconfigurable resources and flash memory, allows for a speed-up factor of 45 as compared to existing software solutions.
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Dates et versions

inria-00453946 , version 1 (06-02-2010)

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  • HAL Id : inria-00453946 , version 1

Citer

Chikhi Rayan, Steven Derrien, Noumsi Auguste, Patrice Quinton. Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval. International Journal of Electronics, 2008, 95 (7), pp.621-635(15). ⟨inria-00453946⟩
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