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Reports (Research Report) Year : 2009

Proposition for a sequential accelerator in future general-purpose manycore processors

Pierre Michaud
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Yiannakis Sazeides
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André Seznec


The number of transistors that can be put on a given silicon area doubles on every technology generation. Consequently, the number of on-chip cores increases quickly, making it possible to build general-purpose processors with hundreds of cores in a near future. However, though having a large number of cores is beneficial for speeding up parallel code sections, it is also important to speed up sequential execution. We argue that it will be possible and desirable to dedicate a large fraction of the chip area and power to high sequential performance. Current processor design styles are restrained by the implicit constraint that a processor core should be able to run continuously; therefore power hungry techniques that would allow very high clock frequencies are not used. The "sequential accelerator" we propose removes the constraint of continuous functioning. The sequential accelerator consists of several cores designed for ultimate instantaneous performance. Those cores are large and power hungry, they cannot run continuously (thermal constraint) and cannot be active simultaneously (power constraint) . A single core is active at any time, inactive cores are power-gated. The execution is migrated periodically to a new core so as to spread the heat generation uniformly over the whole accelerator area, which solves the temperature issue. The "sequential accelerator" will be a viable solution only if the performance penalty due to migrations can be tolerated. Migration-induced cache misses may incur a significant performance loss. We propose some solutions to alleviate this problem. We also propose a migration method, using integrated thermal sensors, such that the migration interval is variable and depends on the ambient temperature. The migration penalty can be kept negligible as long as the ambient temperature is maintained below a threshold.
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Dates and versions

inria-00433234 , version 1 (18-11-2009)
inria-00433234 , version 2 (19-11-2009)
inria-00433234 , version 3 (10-12-2009)


  • HAL Id : inria-00433234 , version 3


Pierre Michaud, Yiannakis Sazeides, André Seznec. Proposition for a sequential accelerator in future general-purpose manycore processors. [Research Report] RR-7106, INRIA. 2009. ⟨inria-00433234v3⟩
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