A Hardware Processing Unit for Point Sets - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2008

A Hardware Processing Unit for Point Sets


We present a hardware architecture and processing unit for point sampled data. Our design is focused on fundamental and computationally expensive operations on point sets including k-nearest neighbors search, moving least squares approximation, and others. Our architecture includes a configurable processing module allowing users to implement custom operators and to run them directly on the chip. A key component of our design is the spatial search unit based on a kd-tree performing both kNN and eN searches. It utilizes stack recursions and features a novel advanced caching mechanism allowing direct reuse of previously computed neighborhoods for spatially coherent queries. In our FPGA prototype, both modules are multi-threaded, exploit full hardware parallelism, and utilize a fixed-function data path and control logic for maximum throughput and minimum chip surface. A detailed analysis demonstrates the performance and versatility of our design.
No file

Dates and versions

inria-00354990 , version 1 (21-01-2009)


  • HAL Id : inria-00354990 , version 1


Simon Heinzle, Gael Guennebaud, Mario Botsch, Markus Gross. A Hardware Processing Unit for Point Sets. Graphics Hardware 2008, Jun 2008, Sarajevo, Bosnia and Herzegovina. pp.21-31. ⟨inria-00354990⟩
35 View
0 Download


Gmail Facebook X LinkedIn More