On-Line Arithmetic Based Reprogrammable Hardware Implementation of LVQ Neural Network for Alertness Classification - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Journal Articles International Journal of Computer Science and Network Security Year : 2008

On-Line Arithmetic Based Reprogrammable Hardware Implementation of LVQ Neural Network for Alertness Classification

Abstract

The current study presents the hardware implementation of a learning Vector Quantization (LVQ) neural network. Starting from the spectral EEG analysis, we suggest an LVQ serial on-line architecture implementation on a Field programmable Gate Array (FPGA) circuit. Our concern was mainly to get a light, easy-to-wear system for the classification of vigilance levels in humans using EEG signals. The results of these classified states by LVQ mode are presented in this paper. Furthermore, the highly satisfactory performances of our implementation in terms of area speed and delay are described.
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Dates and versions

inria-00338767 , version 1 (14-11-2008)

Identifiers

  • HAL Id : inria-00338767 , version 1

Cite

M. Boubaker, Khaled Ben Khalifa, Bernard Girau, Mohamed Dogui, Mohamed Hédi Bedoui. On-Line Arithmetic Based Reprogrammable Hardware Implementation of LVQ Neural Network for Alertness Classification. International Journal of Computer Science and Network Security, 2008, 8 (3), pp.260-266. ⟨inria-00338767⟩
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