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Reports (Research Report) Year : 2008

Clock Constraints in UML/MARTE CCSL


The UML Profile for Modeling and Analysis of Real-Time and Embedded (RTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by UML2 and offers a broad range of capabilities required to model RTE systems including both discrete/dense and chronometric/logical time. MARTE OMG specification introduces a Time Structure inspired from Time models of the concurrency theory and proposes a new Clock Constraint Specification Language (CCSL) to specify, within the context of UML, usual logical and chronometric time constraints. This paper presents, for the first time, the formal semantics of some representative CCSL clock constraints concerning logical discrete-time. Considering the Time Structure as a concurrent system, we propose a dynamic interpretation to build acceptable solutions that fully respect the constraints. An unusual example about processing Easter days illustrates the use of CCSL and the construction of solutions.
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Dates and versions

inria-00280941 , version 1 (20-05-2008)
inria-00280941 , version 2 (22-05-2008)


  • HAL Id : inria-00280941 , version 2


Charles André, Frédéric Mallet. Clock Constraints in UML/MARTE CCSL. [Research Report] RR-6540, INRIA. 2008. ⟨inria-00280941v2⟩
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