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Conference Papers Year : 2007

Hardware/Software Codesign for Embedded Implementations of Neural Networks


The performance of configurable digital circuits such as Field Programmable Gate Arrays (FPGA) increases at a very fast rate. Their fine-grain parallelism shows great similarities with connectionist models. This is the motivation for numerous works of neural network implementations on FPGAs, targeting applications such as autonomous robotics, ambulatory medical systems, etc. Nevertheless, such implementations are performed with an ASPC approach that requires a strong hardware expertise. In this paper a hardware/software codesign framework devoted to FPGA-based design and implementations of neural networks from high level specifications is presented. Such a framework aims at providing the connectionist community with efficient automatic FPGA implementations of their models without any advanced knowledge of hardware. The framework is capable of representing most standard or classical neural topologies. The internal representation of a neural model is bound to commonly used hardware computing units in a library to create the hardware model. A current developed software platform, NNetWARE-Builder, handles multilayer feedforward neural networks and graphically-designed networks of neurons and automatically compiles them onto FPGA devices with third party tools. Experimental results are presented to evaluate design and implementation tradeoffs.
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inria-00173741 , version 1 (20-09-2007)


  • HAL Id : inria-00173741 , version 1


César Torres-Huitzil, Bernard Girau, Adrien Gauffriau. Hardware/Software Codesign for Embedded Implementations of Neural Networks. Applied Reconfigurable Computing, Mar 2007, Rio de Janeiro, Brazil. ⟨inria-00173741⟩
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