Formal Methods for Schedulings of Latency-Insensitive Designs - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Reports (Research Report) Year : 2007

Formal Methods for Schedulings of Latency-Insensitive Designs


LID ( Latency-Insensitive Design) theory was invented to deal with SoC timing closure issues, by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with using a resynchronization protocol that performs dynamic scheduling of data transportation. Functional behaviour is preserved. This dynamic scheduling is implemented using specific synchronous hardware elements: Relay-Stations (RS) and Shell-Wrappers (SW). Our first goal is to provide a formal modeling of RS and SW, that can then be formally verified. As turns out, resulting behaviour is k-periodic, thus amenable to static scheduling. Our second goal is to provide formal hardware modeling here also. It initially performs Throughput Equalization, adding integer latencies wherever possible; residual cases require introduction of Fractional Registers (FRs) at specific locations. Benchmark results are presented, run on our KPassa tool implementation.
Fichier principal
Vignette du fichier
RR-6149.pdf (344.45 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

inria-00137495 , version 1 (22-03-2007)
inria-00137495 , version 2 (22-03-2007)


  • HAL Id : inria-00137495 , version 2


Julien Boucaron, Jean-Vivien Millo, Robert de Simone. Formal Methods for Schedulings of Latency-Insensitive Designs. [Research Report] RR-6149, INRIA. 2007, pp.25. ⟨inria-00137495v2⟩
131 View
152 Download


Gmail Facebook Twitter LinkedIn More