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Journal Articles International Journal of Neural Systems Year : 2000

FPNA: interaction between FPGA and neural computation

Bernard Girau


Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. A theoretical and practical framework called FPNA allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.
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inria-00099134 , version 1 (26-09-2006)


  • HAL Id : inria-00099134 , version 1


Bernard Girau. FPNA: interaction between FPGA and neural computation. International Journal of Neural Systems, 2000, 10 (3), pp.243-259. ⟨inria-00099134⟩
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