Microcoding an abstract machine for parallel logic programming
Abstract
This paper shows the advantages of implementing an abstract intermediate machine for a parallel logical language, on the lower hardware level the FIRMWARE level - of a physical machine which implements basic hardware mechanisms for fast symbolic computation. µSyC, which is a µprogrammable Symbolic Coprocessor under development at the Bull Research Center, has been chosen as a target architecture and the abstract machine in question is the Sequential Parlog Machine which is based on the AND/OR tree execution model for concurrent logical languages such as PARLOG, CP and GHC. The paper describes the µSyC architecture, the language PARLOG, the AND/OR tree model, and the mapping of this model on µSyC. Finally, results for a series of classical benchmark tests is given and compared to other available implementations.