Multiple-Block Ahead Branch Predictors - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Reports (Research Report) Year : 1996

Multiple-Block Ahead Branch Predictors


A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. To overcome the instruction fetch bottleneck shown in wide-dispatch «brainiac» processors, this paper presents a novel cost-effective mechanism called the multiple-block ahead branch predictor that predicts in an efficient way addresses of multiple basic blocks in a single cycle. Moreover and unlike the previous multiple predictor schemes, the multiple-block ahead branch predictor can use any of the branch prediction schemes to perform very accurate predictions required to achieve high-performance on superscalar processors. Finally, we show that pipelining the branch prediction process can be done by means of our predictor for «speed demon» processors to achieve higher clock rate.


Other [cs.OH]
Fichier principal
Vignette du fichier
RR-2825.pdf (298.53 Ko) Télécharger le fichier

Dates and versions

inria-00073867 , version 1 (24-05-2006)


  • HAL Id : inria-00073867 , version 1


André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud. Multiple-Block Ahead Branch Predictors. [Research Report] RR-2825, INRIA. 1996. ⟨inria-00073867⟩
207 View
979 Download


Gmail Facebook Twitter LinkedIn More