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Reports (Research Report) Year : 1997

Tiling with Limited Resources


In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformati- on. Little work has been devoted to the mapping and scheduling of the tiles on to physical processors. We present several new results in the context of limited computational resources, and assuming communication-computation overlap. In particular, under some reasonable assumptions, we derive the optimal mapping and scheduling of tiles to physical processors.


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Dates and versions

inria-00073506 , version 1 (24-05-2006)


  • HAL Id : inria-00073506 , version 1


Pierre-Yves Calland, Jack Dongarra, Yves Robert. Tiling with Limited Resources. [Research Report] RR-3183, INRIA. 1997. ⟨inria-00073506⟩
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