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Reports (Research Report) Year : 2005

A Case for a Complexity-Effective, Width-partitioned Microarchitecture

Abstract

Current superscalar processors feature 64-bit datapaths to execute the program instructions, regardless of their operands size. Our analysis indicates, however, that most executions comprise a large amount (40%) of narrow-width operations; i.e. instructions which exclusively process narrow-width operands and results. We further noticed that these operations are well distributed across a program run. In this paper, we exploit these properties to master the hardware complexity of superscalar processors. We propose a width-partitioned microarchitecture (WPM) to decouple the treatment of narrow-width operations from that of the other program instructions. We split a 4-way issue processor into two clusters: one executing 64-bit operations, load/store and complex operations and the other treating the 16-bit operations. We show that revealing the narrow-width operations to the hardware is sufficient to keep the workload balanced and the communications minimized between clusters. Using a WPM reduces the complexity of several critical processor components : register file and bypass network. A WPM also lowers the complexity of the interconnection fabric since the 16-bit cluster is only able to propagate narrow-width data. We examine simple configurations of WPM while discussing their tradeoffs. We evaluate a speculative heuristic to steer the narrow-width operations towards clusters. A detailed complexity analysis shows using a WPM model saves power and area with a minimal impact on performance.
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Dates and versions

inria-00070336 , version 1 (19-05-2006)

Identifiers

  • HAL Id : inria-00070336 , version 1

Cite

Olivier Rochecouste, Gilles Pokam, André Seznec. A Case for a Complexity-Effective, Width-partitioned Microarchitecture. [Research Report] RR-5677, INRIA. 2005, pp.27. ⟨inria-00070336⟩
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