A Flexible Thread Scheduler for Hierarchical Multiprocessor Machines - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2005

A Flexible Thread Scheduler for Hierarchical Multiprocessor Machines

Abstract

With the current trend of multiprocessor machines towards more and more hierarchical architectures, exploiting the full computational power requires careful distribution of execution threads and data so as to limit expensive remote memory accesses. Existing multi-threaded libraries provide only limited facilities to let applications express distribution indications, so that programmers end up with explicitly distributing tasks according to the underlying architecture, which is difficult and not portable. In this article, we present: (1) a model for dynamically expressing the structure of the computation; (2) a scheduler interpreting this model so as to make judicious hierarchical distribution decisions; (3) an implementation within the Marcel user-level thread library. We experimented our proposal on a scientific application running on a ccNUMA Bull NovaScale with 16 Intel Itanium II processors; results show a 30% gain compared to a classical scheduler, and are similar to what a handmade scheduler achieves in a non-portable way.
Fichier principal
Vignette du fichier
coset.pdf (149.35 Ko) Télécharger le fichier
Loading...

Dates and versions

inria-00000138 , version 1 (27-06-2005)

Identifiers

Cite

Samuel Thibault. A Flexible Thread Scheduler for Hierarchical Multiprocessor Machines. Second International Workshop on Operating Systems, Programming Environments and Management Tools for High-Performance Computing on Clusters (COSET-2), ICS / ACM / IRISA, Jun 2005, Cambridge, United States. ⟨inria-00000138⟩
117 View
172 Download

Altmetric

Share

Gmail Facebook Twitter LinkedIn More