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Communication Dans Un Congrès Année : 2022

Design of a Reconfigurable Optical Computing Architecture Using Phase Change Material

Parya Zolfaghari
  • Fonction : Auteur
  • PersonId : 1342380
Sébastien Le Beux
  • Fonction : Auteur
  • PersonId : 1121965

Résumé

Silicon photonics is an emerging technology allowing to take the advantage of high-speed light propagation to accelerate computing kernels in integrated systems. Micrometer-scale optical devices call for reconfigurable architectures to maximize resources utilization. Typical reconfigurable optical computing architectures involve micro-ring resonators for electro-optic modulation. However, such devices require voltage and thermal tuning to compensate for fabrication process variability and thermal sensitivity. This power-hungry calibration leads to significant static power overhead, thus limiting the scalability of optical architectures. In this chapter, we propose to use non-volatile Phase Change Materials (PCM) elements to route optical signals only through the required resonators, hence saving calibration energy of bypassed resonators. The non-volatility of PCM elements allows maintaining the optical path. We investigate the efficiency of the PCM elements on the Reconfigurable Directed Logic (RDL) architecture. We also evaluate the static power saving induced by the use of couplers instead of microring to redirect WDM signals into a single waveguide. Finally, we show that the couplers can be efficiently used to cascade the architectures, allowing to increase the number of inputs to be processed without opto-electronic conversions. Compared to a ring-based implementation of RDL architecture, results show that the proposed implementation allows reducing the static power by 53% on average.
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Dates et versions

hal-04419567 , version 1 (26-01-2024)

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Parya Zolfaghari, Sébastien Le Beux. Design of a Reconfigurable Optical Computing Architecture Using Phase Change Material. 29th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2021, Singapore, Singapore. pp.155-174, ⟨10.1007/978-3-031-16818-5_8⟩. ⟨hal-04419567⟩
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