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Comet: a RISC-V Core Synthesized from C++ Specifications


Designing the hardware of a processor core as well as its verification flow from a single high-level specification provides great advantages in terms of productivity and maintainability. In this work, we highlight the Comet RISC-V core specified from a unique C++ model. The same code is used to generate both the hardware target design through High-Level Synthesis as well as a fast and cycle-accurate bit-accurate simulator of the latter through software compilation. The object oriented nature of C++ greatly improves the readability and flexibility of the design description compared to classical HDLbased implementations. Therefore, the processor model can easily be modified, expanded and verified using standard software development methodologies. Previous work demonstrated that the core frequency and area of the generated hardware are comparable to existing RTL implementations [1]. In this poster we present the status and roadmap around Comet.
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Dates and versions

hal-03885663 , version 1 (05-12-2022)




  • HAL Id : hal-03885663 , version 1


Simon Rokicki, Joseph Paturel, Olivier Sentieys. Comet: a RISC-V Core Synthesized from C++ Specifications. Spring 2022 RISC-V Week, May 2022, Paris, France. ⟨hal-03885663⟩
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