Automatic Flat-Level Circuit Generation with Genetic Algorithms - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2020

Automatic Flat-Level Circuit Generation with Genetic Algorithms

Résumé

This paper describes a novel methodology to generate analog and digital circuits, autonomously, using the transistor (or other elementary device, e.g. resistor) as the basic elementary block – flat-level. A genetic algorithm is employed as the generation engine and variable length chromosomes are used to describe the circuit topology that evolves during the search. The circuit devices type and sizing are described by each gene of genetic algorithm. The automatic process starts with the circuit input and output specifications, and proceeds with the circuit topology and sizing evolution to meet those specifications, eventually, ending up with a novel topology. During the evolution, each generated circuit is electrically evaluated by a spice-like circuit simulator, i.e. Ngspice, using full model specifications - like BSIM3 for transistors - in a highly parallelized architecture built over a multi-thread model.
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hal-03741565 , version 1 (01-08-2022)

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Miguel Campilho-Gomes, Rui Tavares, João Goes. Automatic Flat-Level Circuit Generation with Genetic Algorithms. 11th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Jul 2020, Costa de Caparica, Portugal. pp.101-108, ⟨10.1007/978-3-030-45124-0_9⟩. ⟨hal-03741565⟩
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