Distributed-memory multi-GPU block-sparse tensor contraction for electronic structure - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2021

Distributed-memory multi-GPU block-sparse tensor contraction for electronic structure

Résumé

Many domains of scientific simulation (chemistry, condensed matter physics, data science) increasingly eschew dense tensors for block-sparse tensors, sometimes with additional structure (recursive hierarchy, rank sparsity, etc.). Distributedmemory parallel computation with block-sparse tensorial data is paramount to minimize the time-to-solution (e.g., to study dynamical problems or for real-time analysis) and to accommodate problems of realistic size that are too large to fit into the host/device memory of a single node equipped with accelerators. Unfortunately, computation with such irregular data structures is a poor match to the dominant imperative, bulk-synchronous parallel programming model. In this paper, we focus on the critical element of block-sparse tensor algebra, namely binary tensor contraction, and report on an efficient and scalable implementation using the task-focused PaRSEC runtime. High performance of the block-sparse tensor contraction on the Summit supercomputer is demonstrated for synthetic data as well as for real data involved in electronic structure simulations of unprecedented size.
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Dates et versions

hal-03508930 , version 1 (03-01-2022)

Identifiants

Citer

Thomas Herault, Yves Robert, George Bosilca, Robert J Harrison, Cannada A Lewis, et al.. Distributed-memory multi-GPU block-sparse tensor contraction for electronic structure. IPDPS 2021 - IEEE International Parallel and Distributed Processing Symposium, May 2021, Portland, OR, United States. pp.1-10, ⟨10.1109/IPDPS49936.2021.00062⟩. ⟨hal-03508930⟩
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