BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Journal Articles IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Year : 2022

BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation

Abstract

Since several decades, fault tolerance has become a major research field due to transistor shrinking and core number increasing in System-on-Chip (SoC). Especially, faults occurring to Network-on-Chips (NoCs) of those systems have a significant impact, due to the high amount of data, crossing the NoC, for the communication among Intellectual Properties (IPs). Furthermore, existing fault tolerant approaches cannot efficiently deal with several permanent faults, which occur in NoC routers. To address these limitations, we propose the Bit Shuffling meThod (BiSuT) for fault tolerant NoCs that reduces the impact of faults on data communications. To achieve that, the proposed approach exploits, at run-time, the position of permanent faults and changes the order of bits inside a flit. Our method reduces, as much as possible, the impact of faults by transferring the faults on Least Significant Bits (LSBs), instead of keeping them on Most Significant Bits (MSBs). The results obtained by extensive evaluations show that BiSuT can reduce the impact of multiple permanent faults, with low hardware costs, compared to existing approaches, like Hamming code.
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Dates and versions

hal-03379489 , version 1 (15-10-2021)

Identifiers

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Romain Mercier, Cedric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet. BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41 (7), pp.2276-2289. ⟨10.1109/TCAD.2021.3101406⟩. ⟨hal-03379489⟩
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