Resource Optimal Truncated Multipliers for FPGAs - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2021

Resource Optimal Truncated Multipliers for FPGAs

Abstract

This proposal presents the resource optimal design of truncated multipliers targeting field programmable gate arrays (FPGAs). In contrast to application specific integrated circuits (ASICs), the design for FPGAs has some distinct design challenges due to many possibilities of computing the partial products using logic-based or DSP-based sub-multipliers. To tackle this, we extend a previously proposed tiling methodology which translates the multiplier design into a geometrical problem: the target multiplier is represented by a board that has to be covered by tiles representing the sub-multipliers. The tiling with the least resources can be found with integer linear programming (ILP). Our extension considers the error of possibly unoccupied positions of the board and determines the tiling with the least resources that respects the maximal allowed error bound. This error bound is chosen such that a faithfully rounded truncated multiplier is obtained. Compared to previous designs that use a fixed number of guard bits or optimize at the level of the dot diagrams, this allows a much better use of sub-multipliers resulting in significant area savings without sacrificing the timing.
Fichier principal
Vignette du fichier
main.pdf (350.02 Ko) Télécharger le fichier
Origin Files produced by the author(s)

Dates and versions

hal-03220290 , version 1 (07-05-2021)

Identifiers

Cite

Andreas Böttcher, Martin Kumm, Florent de Dinechin. Resource Optimal Truncated Multipliers for FPGAs. ARITH 2021 - 28th IEEE International Symposium on Computer Arithmetic, Jun 2021, Torino, Italy. pp.1-8, ⟨10.1109/ARITH51176.2021.00029⟩. ⟨hal-03220290⟩
101 View
387 Download

Altmetric

Share

Gmail Mastodon Facebook X LinkedIn More