SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores

Anita Tino; Caroline Collange; André Seznec

doi:10.1145/3392032

Journal Articles ACM Transactions on Architecture and Code Optimization Year : 2020

SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores

(1, 2) , (2) , (2)

1
2

Anita Tino

Function : Author

Simon Fraser University = Université Simon Fraser

Pushing Architecture and Compilation for Application Performance

Caroline Collange

Function : Author
PersonId : 177452
IdHAL : caroline-collange
IdRef : 151116776

Pushing Architecture and Compilation for Application Performance

André Seznec

Function : Author
PersonId : 13729
IdHAL : andre-seznec
ORCID : 0000-0002-3058-6503
IdRef : 033236402

Pushing Architecture and Compilation for Application Performance

Keywords

Out-of-Order computer architecture multi-threading SIMT Micro-architecture hardware

Domains

Hardware Architecture [cs.AR]

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Tino_SIMT-X_TACO20.pdf (434.21 Ko)

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Caroline Collange : Connect in order to contact the contributor

https://inria.hal.science/hal-02542333

Submitted on : Tuesday, April 14, 2020-4:33:50 PM

Last modification on : Wednesday, April 3, 2024-11:42:03 AM

Dates and versions

hal-02542333 , version 1 (14-04-2020)

Identifiers

HAL Id : hal-02542333 , version 1
DOI : 10.1145/3392032

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Anita Tino, Caroline Collange, André Seznec. SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores. ACM Transactions on Architecture and Code Optimization, 2020, 17 (2), pp.15. ⟨10.1145/3392032⟩. ⟨hal-02542333⟩

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SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores

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