Worst-Case Reaction Time Optimization on Deterministic Multi-Core Architectures with Synchronous Languages - Inria - Institut national de recherche en sciences et technologies du numérique
Conference Papers Year : 2019

Worst-Case Reaction Time Optimization on Deterministic Multi-Core Architectures with Synchronous Languages

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Embedded Systems Hardware Architecture [cs.AR] Computation and Language [cs.CL]
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https://inria.hal.science/hal-02400009

Submitted on : Monday, December 9, 2019-12:35:21 PM

Last modification on : Friday, December 6, 2024-3:19:53 AM

Long-term archiving on : Tuesday, March 10, 2020-5:39:05 PM

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hal-02400009 , version 1 (09-12-2019)

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Nicolas Hili, Alain Girault, Eric Jenn. Worst-Case Reaction Time Optimization on Deterministic Multi-Core Architectures with Synchronous Languages. 25th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'19), Aug 2019, Hangzhou, China. pp.10, ⟨10.1109/RTCSA.2019.8864570⟩. ⟨hal-02400009⟩

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