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Conference Papers Year : 2017

Simty: generalized SIMT execution on RISC-V

Abstract

We present Simty, a massively multi-threaded RISC-V processor core that acts as a proof of concept for dynamic inter-thread vector-ization at the micro-architecture level. Simty runs groups of scalar threads executing SPMD code in lockstep, and assembles SIMD instructions dynamically across threads. Unlike existing SIMD or SIMT processors like GPUs or vector processors, Simty vector-izes scalar general-purpose binaries. It does not involve any instruction set extension or compiler change. Simty is described in synthesizable RTL. A FPGA prototype validates its scaling up to 2048 threads per core with 32-wide SIMD units. Simty provides an open platform for research on GPU micro-architecture, on hybrid CPU-GPU micro-architecture, or on heterogeneous platforms with throughput-optimized cores.

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Dates and versions

hal-01622208 , version 2 (07-10-2020)
hal-01622208 , version 3 (08-02-2022)

Identifiers

  • HAL Id : hal-01622208 , version 3

Cite

Caroline Collange. Simty: generalized SIMT execution on RISC-V. CARRV 2017 - 1st Workshop on Computer Architecture Research with RISC-V, Oct 2017, Boston, United States. pp.6. ⟨hal-01622208v3⟩
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