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Conference Papers Year : 2011

A Novel Chaining Approach to Indirect Control Transfer Instructions


Both dynamic binary translation systems and optimization systems store the translated or optimized code in the software maintained code cache for reuse. The performance of the code cache is crucial. Translated code is usually organized as code blocks in the code cache and each code block transfer control to the next one through a control transfer instruction. As the target address of a control transfer instruction is in the form of its source program counter, the conventional code cache system has to check the address mapping table for the translated target address to find the required target code block, which will cause considerable performance degradation. Control transfer instructions can be divided into two categories as direct control transfer instructions and indirect control transfer instructions. For indirect control transfer instructions, the target address is hold in the register or memory element whose content can be changed during the execution of the program. It is difficult to chain the indirect control transfer instructions with a fixed translated target address through pure software approaches. A novel indirect control transfer chaining approach is proposed in this paper. The principle of the technique is to insert custom chaining instructions into the translated code block while translating the indirect control transfer instructions and execute those chaining instructions to implement dynamical chaining. Some special hardware and software assists are proposed in this paper. Evaluation of the proposed approach is conducted on a code cache simulator. Experiment results show that our hardware assisted indirect control transfer instruction chaining approach can improve the performance of the code cache system dramatically.
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Dates and versions

hal-01590412 , version 1 (19-09-2017)





Wei Chen, Zhiying Wang, Qiang Dou, Yongwen Wang. A Novel Chaining Approach to Indirect Control Transfer Instructions. 1st Availability, Reliability and Security (CD-ARES), Aug 2011, Vienna, Austria. pp.309-320, ⟨10.1007/978-3-642-23300-5_24⟩. ⟨hal-01590412⟩
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