A Small Depth-16 Circuit for the AES S-Box - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2012

A Small Depth-16 Circuit for the AES S-Box

Joan Boyar
  • Function : Author
  • PersonId : 1007445


New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].
Fichier principal
Vignette du fichier
978-3-642-30436-1_24_Chapter.pdf (141.68 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-01518214 , version 1 (04-05-2017)





Joan Boyar, René Peralta. A Small Depth-16 Circuit for the AES S-Box. 27th Information Security and Privacy Conference (SEC), Jun 2012, Heraklion, Crete, Greece. pp.287-298, ⟨10.1007/978-3-642-30436-1_24⟩. ⟨hal-01518214⟩
236 View
290 Download



Gmail Facebook Twitter LinkedIn More