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Conference Papers Year : 2013

Software/Hardware Hybrid Network-on-Chip Simulation on FPGA


In this paper, a software-and-hardware hybrid simulation method for CMP (Chip-MultiProcessor) system is designed, as well as its performance model. In detail, the NoC (Network-On-Chip) module is totally simulated by the FPGA resource; a software-and-hardware interaction interface of this module is provided so that the simulation software running on the on-chip soft core can cooperate with the NoC to complete the whole simulation. In other words, the most time-consuming and relatively-fixed part is implemented by hardware and others are implemented by software, which maintains simulation flexibility and high performance owing to the compact on-chip design. We implement this design on the Xilinx’s Virtex 5 155T chip and the work frequency is 100Mhz. Compared with a typical software counterpart, the simulation speed of NoC is more than 3000 times faster; and the advantage is widened further with the increasing injection rate. Moreover, compared with another hybrid method executing the software part on the host CPU, it is still fairly faster although the host performance is much higher than the on-chip core.
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hal-01513775 , version 1 (25-04-2017)





Youhui Zhang, Peng Qu, Ziqiang Qian, Hongwei Wang, Weimin Zheng. Software/Hardware Hybrid Network-on-Chip Simulation on FPGA. 10th International Conference on Network and Parallel Computing (NPC), Sep 2013, Guiyang, China. pp.167-178, ⟨10.1007/978-3-642-40820-5_15⟩. ⟨hal-01513775⟩
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