Superword Level Parallelism aware Word Length Optimization - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2017

Superword Level Parallelism aware Word Length Optimization

Résumé

Many embedded processors do not support floating-point arithmetic in order to comply with strict cost and power consumption constraints. But, they generally provide support for SIMD as a mean to improve performance for little cost overhead. Achieving good performance when targeting such processors requires the use of fixed-point arithmetic and efficient exploitation of SIMD data-path. To reduce time-to-market, automatic SIMDization – such as superword level parallelism (SLP) extraction – and float-to-fixed-point conversion methodologies have been proposed. In this paper we show that applying these transformations independently is not efficient. We propose a SLP-aware word length optimization algorithm to jointly perform float-to-fixed-point conversion and SLP extraction. We implement the proposed approach in a source-to-source compiler framework and evaluate it on several embedded processors. Experimental results illustrate the validity of our approach.
Fichier principal
Vignette du fichier
main.pdf (575.62 Ko) Télécharger le fichier
Origine Fichiers produits par l'(les) auteur(s)

Dates et versions

hal-01425550 , version 1 (03-01-2017)

Identifiants

  • HAL Id : hal-01425550 , version 1

Citer

Ali Hassan El Moussawi, Steven Derrien. Superword Level Parallelism aware Word Length Optimization. Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Mar 2017, Lausanne, Switzerland. ⟨hal-01425550⟩
216 Consultations
264 Téléchargements

Partager

More