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Conference Papers Year : 2015

A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm


Stochastic detection for multi-antenna (MIMO) systems promises communications performance close to max-log detection for certain SNR regimes, especially when the system iterates between detector and channel decoder following the Turbo Principle. In this work, we propose a parallel VLSI architecture for soft-input soft-output Markov chain Monte Carlo based stochastic MIMO detection. It features run-time adaptability to varying channel conditions, effectively allowing us to adjust the invested effort. Besides the details of our area-throughput efficient design, like the low-level algorithm and micro-architecture design, we also provide an extensive data set from our experiments regarding the detector’s communications performance and relate it to our VLSI implementation results. The provided data analysis highlights the architecture’s run-time adaptability and demonstrates how we can trade off throughput for improved communications performance.
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Dates and versions

hal-01383734 , version 1 (19-10-2016)





Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid. A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm. 22th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC 2014), Oct 2014, Playa del Carmen, Mexico. pp.149-169, ⟨10.1007/978-3-319-25279-7_9⟩. ⟨hal-01383734⟩
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