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Sequential PDEVS Architecture


Parallel Discrete Event System Specification (PDEVS) is a well-known formalism used to model and simulate Discrete Event Systems. This formalism uses an abstract simulator that defines a set of abstract algorithms that are parallel by nature. To implement simulators using these abstract algorithms , several architectures were proposed. Most of these architectures follow distributed approaches that may not be appropriate for single core processors or microcontrollers. In order to reuse efficiently PDEVS models in this type of systems, we define a new architecture that provides a single threaded execution by passing messages in a call/return fashion to simplify the execution time analysis.
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hal-01274279 , version 1 (19-02-2016)




  • HAL Id : hal-01274279 , version 1


Damián Vicino, Daniella Niyonkuru, Gabriel Wainer, Olivier Dalle. Sequential PDEVS Architecture. Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium , 2015, Alexandria, Virginia, United States. ⟨hal-01274279⟩
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