Malleable task-graph scheduling with a practical speed-up model - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Reports (Research Report) Year : 2016

Malleable task-graph scheduling with a practical speed-up model


Scientific workloads are often described by Directed Acyclic task Graphs. Indeed, DAGs represent both a model frequently studied in theoretical literature and the structure employed by dynamic runtime schedulers to handle HPC applications. A natural problem is then to compute a makespan-minimizing schedule of a given graph. In this paper, we are motivated by task graphs arising from multifrontal factorizations of sparsematrices and therefore work under the following practical model. We focus on malleable tasks (i.e., a single task can be allotted a time-varying number of processors) and specifically on a simple yet realistic speedup model: each task can be perfectly parallelized, but only up to a limited number of processors. We first prove that the associated decision problem of minimizing the makespan is NP-Complete. Then, we study a widely used algorithm, PropScheduling, under this practical model and propose a new strategy GreedyFilling. Even though both strategies are 2-approximations, experiments on real and synthetic data sets show that GreedyFilling achieves significantly lower makespans.
Fichier principal
Vignette du fichier
RR-8856.pdf (1.11 Mo) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-01274099 , version 1 (15-02-2016)


  • HAL Id : hal-01274099 , version 1


Loris Marchal, Bertrand Simon, Oliver Sinnen, Frédéric Vivien. Malleable task-graph scheduling with a practical speed-up model. [Research Report] RR-8856, ENS de Lyon. 2016. ⟨hal-01274099⟩
287 View
371 Download


Gmail Facebook X LinkedIn More