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Conference Papers Year : 2016

Cost Effective Physical Register Sharing

Arthur Perais
André Seznec

Abstract

Sharing a physical register between several instructions is needed to implement several microarchitectural optimizations. However, register sharing requires modifications to the register reclaiming process: Committing a single instruction does not guarantee that the physical register allocated to the previous mapping of its architectural destination register is free-able anymore. Consequently, a form of register reference counting must be implemented. While such mechanisms (e.g., dependency matrix, per register counters) have been described in the literature, we argue that they either require too much storage, or that they lengthen branch misprediction recovery by requiring sequential rollback. As an alternative, we present the Inflight Shared Register Buffer (ISRB), a new structure for register reference counting. The ISRB has low storage overhead and lends itself to checkpoint-based recovery schemes, therefore allowing fast recovery on pipeline flushes. We illustrate our scheme with Move Elimination (short-circuiting moves) and an implementation of Speculative Memory Bypassing (short-circuiting store-load pairs) that makes use of a TAGE-like predictor to identify memory dependencies. We show that the whole potential of these two mechanisms can be achieved with a small register tracking structure.
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Dates and versions

hal-01259137 , version 1 (19-01-2016)
hal-01259137 , version 2 (20-04-2016)

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Arthur Perais, André Seznec. Cost Effective Physical Register Sharing. International Symposium on High Performance Computer Architecture, IEEE, Mar 2016, Barcelona, Spain. ⟨10.1109/HPCA.2016.7446105⟩. ⟨hal-01259137v2⟩
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