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Logical Clock Constraint Specification in PVS


The Clock Constraint Specification Language (CCSL), first introduced as a companion language for Modeling and Analysis of Real-Time and Embedded systems (MARTE), has now evolved beyond the time specification of MARTE, and has become a full-fledged domain specific modeling language widely used in many domains. This report demonstrates the encoded PVS (Prototype Verification System) theories for interpreting clock relation and clock expression based on schedules as a sequence of clock set. In order to ensure the correctness of the encodings, we prove some interesting properties about the clock constraint. Finally, we give an example to illustrate the approach.
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hal-01192839 , version 1 (03-09-2015)


  • HAL Id : hal-01192839 , version 1


Qingguo Xu, Robert de Simone, Julien Deantoni. Logical Clock Constraint Specification in PVS. [Research Report] 8748, Inria Sophia Antipolis. 2015, pp.11. ⟨hal-01192839⟩
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